High Speed FIR Filters for Digital Decimation
نویسندگان
چکیده
This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.
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تاریخ انتشار 1999